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Naoki Fujieda

Affiliation Department of Electrical and Electronic Information Engineering
Title Assistant Professor
Fields of Research Computer Architecture / FPGA Application / Embedded System / Secure Processor
Degree Doctor of Engineering (Tokyo Institute of Technology)
Academic Societies IPSJ / IEICE / IEEE
E-mail fujieda@ee
Please append ".tut.ac.jp" to the end of the address above.
Laboratory website URL http://meta.ccs.ee.tut.ac.jp/ich/

Research

 The needs for computer systems have been diversified and specialized in recent years. For example, we can develop a processor or a system that performs quite well for a specific application by converting a part of processing of that application into a dedicated logic circuit. We can also give processors additional value that is too costly to be implemented on general-purpose processors... I'm working on processor architecture and applied FPGA system with a keyword of "making processors interesting."

 The most characteristic topic of my research is a secure processor, which improves the protection of software from analysis, plagiarism, and falsification, i.e. tamper resistance. My themes on this topic includes diversification of processors using reconfigurable logic circuits such as FPGAs, and oblivious RAM that hides the access pattern to external memories.

Theme1:Obfuscation of instruction sequences based on instruction set randomization

Overview
The concept of instruction register files

For techniques that improve tamper resistance of embedded systems, it is required to minimize their cost such as loss of performance and increase of hardware resource usage. Encryption of instruction sequences is an obvious solution for software protection, while it may not be the best choice in the sense of cost. In this theme, instruction sequences are efficiently protected with a minimum cost by shuffling (randomizing) instruction set, or relation between instruction and machine language.
In particular, we use an instruction register file (IRF) as a component of our method. Although the IRF is originally proposed to reduce the energy consumption of processors, it can be used as improce tamper resistance. The IRF is a table that memorizes the most frequently executed instructions, which can be compared with a “speed dial” of phones. The analysis of instruction sequences can be obstructed by shuffling its assignment. We have produced some results about an efficient use of the IRF for low-cost software protection.

Selected publications and works

・Naoki Fujieda, Tasuku Tanaka, and Shuichi Ichikawa: Design and Implementation of Instruction Indirection for Embedded Software Obfuscation, Microprocessors and Microsystems, Vol. 45, Part A, pp.115–128 (08/2016).
・Naoki Fujieda, Kiyohiro Sato, and Shuichi Ichikawa: A complement to Enhanced Instruction Register File against Embedded Software Falsification, 5th Program Protection and Reverse Engineering Workshop (PPREW-5), No. 3 (12/2015).
・Naoki Fujieda and Shuichi Ichikawa: Enhanced Instruction Register Files for Embedded Software Obfuscation, 29th International Conference on Computers and Their Applications (CATA-2014), pp. 153–158 (03/2014).

Keywords

Embedded system / Secure processor / Instruction set randomization

Title of class

Experimental Practice for Electrical, Electronic and Information Engineering 1
Experimental Practice for Electrical, Electronic and Information Engineering 2

Others (Awards, Committees, Board members)

See my personal Web site for the list of publication, awards, etc.
https://sites.google.com/site/nfproc


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